1. Field of the Invention
The present invention relates to generating of bandgap voltages, and more particularly, to bandgap reference circuits.
2. Description of the Prior Art
Please refer to FIG. 1. FIG. 1 is a diagram of a bandgap reference circuit 100 according to the prior art. As shown in FIG. 1, the current I1 within the bandgap reference circuit 100 is a current proportional to absolute temperature, where the current is generally referred to as a PTAT current. The current I1 is related to bipolar junction transistors (BJTs) Q1-0, Q1-1, Q1-2, . . . , and Q1-N and is further related to a resistor R1, and can be represented by utilizing the following equation:I1=VT*In(N)/R1.
In the above equation, the thermal voltage VT can be expressed as follows:VT=(k*T)/q; 
where k represents Boltzmann's constant, T represents absolute temperature, and q represents an electric charge equivalent.
In addition, the current I2 within the bandgap reference circuit 100 can be referred to as a complementary to absolute temperature current (i.e. a CTAT current, whose magnitude decreases while absolute temperature increases). The current I2 is related to the BJT Q1-0 and a resistor R2, and can be represented by utilizing the following equation:I2=VEB0/R2;
where VEB0 represents the emitter-base junction voltage of the BJT Q1-0.
The bandgap voltage VREF outputted from the output terminal of the bandgap reference circuit 100 is generated according to a total current (I1+I2), and can be represented by utilizing the following equation:VREF=(I1+I2)*R3=(R3/R2)*(VEB0+(R2/R1)*In(N)*VT).
Please refer to the FIG. 2. FIG. 2 is a diagram of a bandgap reference circuit 200 according to the prior art, where the p-type metal oxide semiconductor (PMOS) transistors M1′, M2′, and M3′ can be respectively implemented by utilizing the PMOS transistors M1, M2, and M3 shown in FIG. 1, the amplifier 210 can be implemented by utilizing the amplifier 110 shown in FIG. 1, and the diodes D2-0, D2-1, D2-2, . . . , and D2-N may be respectively implemented by utilizing the above-mentioned BJTs Q1-0, Q1-1, Q1-2, . . . , and Q1-N. The current I1′ within the bandgap reference circuit 200 can be represented by utilizing the following equation:I1′=ΔVEB′/R1′  (1);
where ΔVEB′ represents the difference between bias voltages of diodes such as bias voltages VD2-0 and VD2-1 (or VD2-2, VD2-3, . . . , VD2-N), and a bias voltage of a diode means the voltage difference between two terminals of the diode. Please note that the voltage VEB′ may represent the voltage difference between two terminals of a diode (e.g., the diode D2-0) in a broad sense, while in a narrow sense, the voltage VEB′ may represent the voltage difference between two terminals of a diode (e.g., the diode D2-0) that is implemented by utilizing the above-mentioned BJT.
In addition, the current I2′ within the bandgap reference circuit 200 can be represented by utilizing the following equation:I2′=(VEB′−VREF′)/R2′  (2);
where VREF′ represents the bandgap voltage outputted from the output terminal of the bandgap reference circuit 200, and can be represented by utilizing the following equation:VREF′=(I1′+3*I2′)*R3′  (3).
Equations (1) and (2) can be substituted into Equation (3) such that the following equation can be obtained:VREF′=C*((R2′/(3*R1′))*ΔVEB′+VEB′)   (4);
where C=(3*R3′)/(R2′+3*R3′). Substitute the equation ΔVEB′=VT*In(N) into Equation (4), another equation can be obtained as follows:VREF′=C*((R2′/(3*R1′))*VT*In(N)+VEB′).
According to the prior art, if the newer architecture shown in FIG. 2 is utilized for generating the bandgap voltage, a sufficiently large circuit area is usually required for implementation of the resistor R2′. More particularly in a low voltage condition, each of the diodes D2-1, D2-2, . . . , and D2-N shown in FIG. 2 need a larger circuit area than that of a normal condition, and the number N is therefore limited and can not be arbitrarily increased in accordance with design requirement(s). As the number N can not be arbitrarily increased, in some situations, it is necessary that a larger circuit area should be utilized for implementing the resistor R2′, causing the economic benefit to be reduced in a mass production phase. Therefore, a novel solution for improving the prior art is required.